1. Technical Field
The embodiment described herein relates to a semiconductor technology and, more particularly, to an internal voltage generating apparatus that performs charge pumping at a is voltage level higher than an external voltage by adopting pumping circuits of two kinds or more.
2. Related Art
A DRAM, which is a semiconductor memory apparatus, generates internal voltages having various voltage levels by using an external voltage and the resultant internal voltages are used for internal operations of the DRAM for each respective purpose.
In the DRAM, a scheme of generating the internal voltage by using the external voltage is generally divided into two scenarios. One scheme of generating the internal voltage is by down-converting the external voltage to a low voltage level. The other scheme generates an internal voltage higher than a level of the external voltage or lower than a ground voltage by pumping the external voltage with a charge pump.
In general, the internal voltage generated by down-converting is used for reducing power consumption and the internal voltage generated by charge pumping is used for a special purpose.
The internal voltage most universally used among the internal voltages of the DRAM, which are generated by charge pumping includes a high voltage VPP and a back-bias voltage VBB.
The high voltage VPP is generated to have a voltage level higher than a power voltage VCC which is the external voltage so as to protect against cell data from being lost at a gate of a cell transistor (or word line) when accessing the cell data.
The back-bias voltage VBB is generated to have a voltage level lower than the ground voltage VSS, which is the external voltage in a bulk of the cell transistor, so as to protect against the loss of data stored in a cell.
Recently, the level of the external voltage of the semiconductor memory apparatus has been lowered to around 1.5V or below. As a result, it is difficult to ensure normal operations of a circuit with levels of the internal voltages used by down-converting the external voltage in order to reduce power in the conventional art.
An example in which the normal operation in the semiconductor memory apparatus is difficult to ensure will be described with reference to FIGS. 1A to 1C.
FIG. 1A illustrates a bit line sense amplifier (hereinafter, referred to as BLSA). In FIG. 1A, a bit line equalizing (hereinafter, referred to as BLEQ) transistor that equalizes a bit line (hereinafter, referred to as BL) and a bit line bar (hereinafter, referred to as /BL) is shown configured. The external voltage level or a voltage level lower than the external voltage level may be adopted in the BLEQ transistor as a pull-up voltage level for controlling a gate. However, in this case, the bit line BL and the bit line bar /BL cannot be normally equalized.
Further, a sense amplifier (hereinafter, referred to as SA) of FIG. 1B also cannot normally perform a precharge operation, before activating a pull-up transistor and a pull-down transistor, when a voltage level used as a pull-up source of a control signal of a transistor that precharges the pull-up and pull-down transistors to a level of a bit line precharge voltage ‘VBLP’ is used as the external voltage or the power voltage lower than the external voltage.
Further, in FIG. 1C, in the situation where a voltage level is used as a pull-up source of a gate of a transistor that precharges between signal lines SIO and /SIO and local input/output lines LIO and /LIO and between the local input/output lines LIO and /LIO and global input/output lines GIO and /GIO so that the voltage level uses the external voltage or the power voltage lower than the external voltage, then the precharge operation cannot also be normally performed.
As described above, with reference to FIGS. 1A to 1C, the reason why the precharge operation cannot be performed in the usual standard ways is that an NMOS transistor is difficult to transmit a high-level voltage of an input terminal because operating characteristics thereof to an output terminal. Also the NMOS transistor loses an electric potential as high as a threshold voltage ‘vth’ at a source thereof in the case when a gate potential is not higher than a drain potential by the threshold voltage ‘vth’ or more and a voltage of the source is applied to a drain.
One method for solving the above-mentioned problem is to use a double charge pump circuit shown in FIG. 2. The double charge pump circuit of FIG. 2 charge-pumps the high voltage VPP, which is the internal voltage to a voltage level higher than the voltage level of the external voltage, and uses the high voltage VPP as the pull-up source. The double charge pump circuit of FIG. 2 includes a VPP level detector 20, a ring oscillator 22, a pump control logic 24, and a doubler charge pump 26.
However, in the scheme of using the double charge pump of FIG. 2, since the efficiency of the charge pump with respect to the power voltage VCC of a low level is low, it then becomes difficult to pump the high voltage VPP which is the internal voltage to a predetermined voltage level or higher and as a result a large amount of current is consumed for pumping. Therefore, this scheme is disadvantageous in terms of current efficiency.
In order to solve the above problem in respects to current consumption, a circuit including the double charge pump and a triple charge pump may be used to generate the high voltage VPP as shown in FIG. 3. As shown in FIG. 3, the circuit of includes a VPP level detector 30, a ring oscillator 31, a pump control logic 32, a tripler charge pump 33, a ring oscillator 34, a pump control logic 35, and a doubler charge pump 36. The ring oscillator 31, the pump control logic 32 and the tripler charge pump 33 for triple pumping are connected to the ring oscillator 34, the pump control logic 35, and the doubler charge pump 36 are in parallel for double pumping. Among them, output terminals of the tripler charge pump 33 and the doubler charge pump 36 share a feed-back path to the VPP level detector 30.
The circuit of FIG. 3 can generate the requisite high voltage VPP at a high level by using the triple charge pump from the external voltage VCC of a low level. The circuit of FIG. 3 also realizes a number of advantages in terms of drivability and efficiency.
However, in situations when the triple charge pump is used in the external voltage VCC of a high level, then too much power is consumed. As a result a large peak-to-peak value is caused by a pumping operation, such that the circuit exhibits an analogical problem.